Twisted ring counters, sometimes variously called cyclic sequential counters or Johnson counters or Moebius counters, are uniquely characterized by operation in accordance with a sequential pattern of states which recurs cyclically, a manner of operation not found, e.g., in binary counters. In that characteristic operation, regular clocking of the counter causes it to step through a normal-mode sequence of stage states in which an all-ONEs pattern of growing size appears to move from input to output and then be replaced by an all-ZEROs pattern of growing size. That cycle repeates continuously. A counter feedback circuit which inverts each bit fed back is instrumental in such performance. These counters are useful in many applications, especially those involving tens of stages, because only relatively simple logic is needed, compared, for example, to binary counters, to detect and output predetermined clock phase conditions.
However, such twisted ring counters are often not used because they are subject to being jumped into disallowed states by noise. A disallowed state is any state not included in the previously outlined repeating sequence, and it is said to be disallowed because in all cases a counter in one of those states is unable by only normal clocking to be returned to its proper sequence; so it is said to operate in an abnormal mode. By the time the faulty condition is discovered and corrected, system disarray can be caused by false outputs provided to counter output utilization circuits. A paper on the subject is "Multimoding and its Supression in Twisted Ring Counters," by W. Bleickardt, and appearing at pages 2029-2050 of the November 1968 Bell System Technical Journal. Bridging-type connections are there taught for use in restoring normal operation after detecting certain criteria which have been found to be common to all abnormal, or disallowed, modes but are not found in a normal mode of operation. Different forms of bridging are needed for different types of counter configurations.
A J. Doron U.S. Pat. No. 4,406,014 shows a switched frequency divider in which bistable devices are connected as a Johnson counter. A NAND gate is provided to detect an incorrect divider state, as indicated by the states of two separated stages, and reset an intermediate stage in an effort at least partially to correct the condition. It can be shown, however, that this technique does not work for all possible incorrect states of all sizes of the divider. For example, in an eight-stage divider, the binary condition 00110011, or its cyclic shifts, would not be detected or corrected because it would never include the 010 or the 101 conditions required by Doron to be in a Johnson operation sequence for correction to take place. In addition, the Doron counter corrects only one stage at a time; but in a noisy environment, additional errors could occur at such a fast rate that the divider may never by completely free of erroneous states.